1. Technical Field
The present invention relates to file information generating method and apparatus that generates file information described in RTL (Register Transfer Level) which includes an interface block at least connected to an external device block, a speed conversion circuit block to be inserted between the interface block and a clock circuit block, and a functional circuit block.
2. Description of the Related Art
In recent years, a method has been developed for performing real-life evaluations through software simulation in order to ensure quality of integrated circuits that are becoming bigger and faster due to technological advancement. In this case, integrated circuits refer to an ASIC (Application Specific Integrated Circuit) and the like.
On the other hand, there is also a method that performs ASIC real-life evaluation without employing software simulation, such as that described in Japanese Patent Laid-Open No. 8-6810. This method performs real-life evaluation by establishing a prototype system of an ASIC equipped with a programmable device such as an FPGA (Field Programmable Gate Array). Recently, this method is becoming the mainstream.
This prototype system is generally established based on a file generated by a circuit engineer using RTL (Register Transfer Level) description. With this method where ASIC real-life evaluation is performed using a prototype system, when an internal speed of the programmable device differs from a speed of connection between an external device, a speed conversion circuit or the like is provided which is designed, for each development of a prototype system, based on the specifications of both the programmable device and the external device.